The present invention relates to a digital matched filter for use in, for example, a spread spectrum communication receiver.
In a so-called direct sequence spread spectrum communication system that transmits an information signal multiplied by a wide-band despreading code and restores a received signal into the original narrow-band information signal by despreading the received signal, the information signal can be detected even when the carrier-to-noise ratio of a received radio wave is degraded. Therefore, the system is full of promise for code division multiple access, which is one of multiple access schemes for mobile communication systems.
According to this direct sequence spread spectrum communication system, the spread received data is despread to be restored to the original state, and therefore, it is required to synchronize the received data with the despreading code sequence. As an index of establishing synchronization, a correlation value of the received data and a despreading code sequence is used. A sum of products of signals of the received data and the corresponding despreading codes in an arbitrary phase is called a correlation value in the phase, and of the correlation values in various phases, the correlation value in a phase where the synchronization of the received data with the despreading code sequence is established takes the maximum value.
Then, the timing of the despreading code sequence can be synchronized to the received data by detecting the phase where the correlation value is maximized. A method using a matched filter is known as one of the methods for obtaining the correlation value in each phase.
FIG. 12 shows the construction of a matched filter of a first prior art example. In FIG. 12, Reference numerals 201 through 208 denote delay elements (DLY) for delaying input data, and the delay elements are connected in series so that the input data are successively shifted in synchronization with the rising edge of a clock. Reference numerals 56 through 63 denote multipliers, which multiply outputs of the delay elements 201 through 208 by the values of codes 1 through 8. In this case, the codes are made to take the value of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. The output of each delay element is multiplied by one in the multipliers 56 through 63 when the value of the code is 0, and the output of each delay element is multiplied by xe2x88x921 when the value of the code is 1. Reference numerals 64 through 70 denote adders, and outputs from the multipliers 56 through 63 are added by these adders 64 through 70 and outputted as output data.
Now, assuming that time domains T1, T2, T3, . . . are delimited in correspondence with the rising or leading edge of the clock, as shown in FIG. 13, and that D1, D2, D3, D4, D5, . . . are supplied as input data, then the contents of the delay elements 201 through 208 and of codes 1 through 8 in the time domains are as shown in FIGS. 14A and 14B, respectively. The input data D1, D2, D3, . . . are sequentially shifted in the delay elements 201 through 208, while the correlation value of the input data and a despreading code sequence of S1 to S8, which is fixed for codes 1 through 8, is calculated.
However, according to the aforementioned conventional construction, the circuit scale for the multipliers is large. In addition, the construction needs a number of multipliers equal to the number of codes in the code sequence. This leads to a problem that the circuit scale increases as the number of codes of the despreading code sequence increases and a problem that downsizing and reduction in consumption of power are hard to achieve.
As a solution to these problems, a technique using exclusive-OR circuits (referred to as xe2x80x98XOR circuitsxe2x80x99 hereinafter) to execute operations equivalent to the multiplication has been proposed (Japanese Patent Laid-Open Publication No. HEI 9-107271).
FIG. 15 shows an example of the construction of a matched filter employing this technique. In FIG. 15, reference numerals 201 through 208 denote delay elements (DLY) for delaying input data, and these delay elements are connected in series so that the input data are successively shifted in synchronization with the rising edge of a clock. Reference numerals 71 through 78 denote XOR circuits, which execute an exclusive-OR operation of the outputs of the delay elements 201 through 208 and the codes 1 through 8. In this case, the codes are made to take the value of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. The output of each delay element is output as it is when the corresponding code has a value of 0, while the output of each delay element is output, with each bit of the data inverted, when the code has a value of 1. Reference numeral 79 denotes an adder, which outputs the number of xe2x80x9c1""sxe2x80x9d included in the codes 1 through 8. Reference numerals 80 through 87 denote adders, which add the outputs of the XOR circuits 71 through 78 and the output of the adder 79, so that the sum is supplied as output data.
In general, in order to multiply data represented by a specified number of bits by xe2x88x921 using a two""s complement, the bits are inverted and then one is added thereto. Thus, by inverting by XOR circuits 71 through 78 each bit of the output of the delay element 201 through 208 corresponding to the code assuming a value of 1, and then adding the value of the code of 1 via the adder 79, operations equivalent to the multiplication of the first prior art of FIG. 12 are achieved.
A part constructed of the XOR circuits 71 and 72 and the adder 80, a part constructed of the XOR circuits 73 and 74 and the adder 81, a part constructed of the XOR circuits 75 and 76 and the adder 82 and a part constructed of the XOR circuits 77 and 78 and the adder 83 are called correlation processors (C.P.) 88 through 91. Assuming that the delay elements 201 through 208 each have a 5-bit output, then the correlation processors 88 through 91 are each constructed of a circuit shown in FIG. 16.
In FIG. 16, input lines A4 through A0 are connected to the bits of the output of the delay element 201 or 203 or 205 or 207, input lines B4 through B0 are connected to the bits of the output of the delay element 202 or 204 or 206 or 208, an input line C is connected to the code 1 or 3 or 5 or 7, and an input line D is connected to the code 2 or 4 or 6 or 8. XOR circuits 92, 93, 94, 95 and 96 represent the XOR circuit 71 or 73 or 75 or 77 bit by bit. These XOR circuits execute an exclusive-OR operation of the signals of the input lines A4 through A0 and the signal of the input line C and output signals G4 through G0. XOR circuits 97, 98, 99, 100 and 101 represent the XOR 72 or 74 or 76 or 78 bit by bit and execute an exclusive-OR operation of the signals of the input lines B4 through B0 and the signal of the input line D, outputting signals H4 through H0.
The signals G4 through G0 and the signals H4 through H0 are added up in circuits 102 through 120 corresponding to the adder 80 or 81 or 82 or 83. An AND circuit 102 and an XOR circuit 107 execute an operation of signals G4 and H4, an AND circuit 103 and an XOR circuit 108 execute an operation of signals G3 and H3, and an AND circuit 104 and an XOR circuit 109 execute an operation of signals G2 and H2. Further, an AND circuit 105 and an XOR circuit 110 execute an operation of signals G1 and H1, and an AND circuit 106 and an XOR circuit 111 execute an operation of signals G0 and H0.
When the XOR circuit 107, 108, 109, 110 has an output of xe2x80x9c0xe2x80x9d, a corresponding selector (SEL) 112, 113, 114, 115 selects the output of the AND circuit 102, 103, 104, 105 to produce an output. When the XOR circuit 107, 108, 109, 110 has an output of xe2x80x9c1xe2x80x9d, the corresponding selector 112, 113, 114, 115 selects the output of the selector 113, 114, 115 or the output of an AND circuit 106, respectively, to produce an output. Carry signals F4, F3, F2, F1 and F0 of the digits are provided by the outputs of the selectors 112 through 115 and the AND circuit 106, and final addition results E5 through E1 are provided by the outputs of XOR circuits 116 through 120 and 111.
Now, assuming that time domains T1, T2, T3, . . . are delimited in correspondence with the rising or leading edge of the clock, as shown in FIG. 13, and that D1, D2, D3, D4, D5, . . . are supplied as input data, then the contents of the delay elements 201 through 208 and of codes 1 through 8 in the time domains are as shown in FIGS. 14A and 14B, respectively. The input data D1, D2, D3, . . . are sequentially shifted in the delay elements 201 through 208, while the correlation value of the input data and a despreading code sequence of S1 to S8, which is fixed for codes 1 through 8, is calculated.
The operation of the correlation processors 88 through 91 will be described herein taking the correlation processor 88 in the time domain T8 as an example. In this case, the bits of input data D8 have been supplied to the respective input lines A4 through A0 of the correlation processor shown in FIG. 16, and the bits of input data D7 have been supplied to the input lines B4 through B0. Further, the despreading code S2 has been supplied to the input line D, and the despreading code S1 has been supplied to the input line C. Assuming that the bits of input data D7 are D74 through D70, that the bits of the input data D8 are D84 through D80 and that i=1 to 4, then carry signals F4 through F0 and addition results E5 through E0 are calculated from the following expressions (1) to (5).                                                         F0              =                              G0                ·                H0                                                                                        =                                                (                                      C                    ⊕                    A0                                    )                                ·                                  (                                      D                    ⊕                    B0                                    )                                                                                                        =                                                (                                      S1                    ⊕                    D80                                    )                                ·                                  (                                      S2                    ⊕                    D70                                    )                                                                                        (        1        )                                                                    Fi              =                              xe2x80x83                            ⁢                                                                                          (                                              Gi                        ⊕                        Hi                                            )                                        _                                    ·                                      (                                          Gi                      ⊕                      Hi                                        )                                                  +                                                      (                                          Gi                      ⊕                      Hi                                        )                                    ·                  Fi                                -                1                                                                                        =                              xe2x80x83                            ⁢                                                                    (                                                                  Gi                        ·                        Hi                                            +                                              Gi                        ·                        Hi                                                              )                                    ·                                      (                                          Gi                      ·                      Hi                                        )                                                  +                                                      (                                          Gi                      ⊕                      Hi                                        )                                    ·                  Fi                                -                1                                                                                        =                              xe2x80x83                            ⁢                                                                                          (                                                                                                    Gi                            _                                                    ·                          Hi                                                +                                                  Gi                          ·                                                      Hi                            _                                                                                              )                                        _                                    ·                                      (                                          Gi                      ·                      Hi                                        )                                                  +                                                      (                                          Gi                      ⊕                      Hi                                        )                                    ·                  Fi                                -                1                                                                                        =                              xe2x80x83                            ⁢                                                Gi                  ·                  Hi                                +                                                      (                                          Gi                      ⊕                      Hi                                        )                                    ·                  Fi                                -                1                                                                                        =                              xe2x80x83                            ⁢                                                                    (                                          C                      ⊕                      Ai                                        )                                    ·                                      (                                          D                      ⊕                      Bi                                        )                                                  +                                                      (                                                                  (                                                  C                          ⊕                          Ai                                                )                                            ⊕                                              (                                                  D                          ⊕                          Bi                                                )                                                              )                                    ·                  Fi                                -                1                                                                                        =                              xe2x80x83                            ⁢                                                                    (                                          S1                      ⊕                      D8i                                        )                                    ·                                      (                                          S2                      ⊕                      D7i                                        )                                                  +                                                      (                                                                  (                                                  S1                          ⊕                          D8i                                                )                                            ⊕                                              (                                                  S2                          ⊕                          D7i                                                )                                                              )                                    ·                  Fi                                -                1                                                                        (        2        )                                                                    E0              =                              G0                ⊕                H0                                                                                        =                                                (                                      C                    ⊕                    A0                                    )                                ⊕                                  (                                      D                    ⊕                    B0                                    )                                                                                                        =                                                (                                      S1                    ⊕                    D80                                    )                                ⊕                                  (                                      S2                    ⊕                    D70                                    )                                                                                        (        3        )                                                                    Ei              =                                                                    (                                          Gi                      ⊕                      Hi                                        )                                    ⊕                  Fi                                -                1                                                                                        =                                                                    (                                          C                      ⊕                      Ai                                        )                                    ⊕                                      (                                          D                      ⊕                      Bi                                        )                                    ⊕                  Fi                                -                1                                                                                        =                                                                    (                                          S1                      ⊕                      D8i                                        )                                    ⊕                                      (                                          S2                      ⊕                      D7i                                        )                                    ⊕                  Fi                                -                1                                                                        (        4        )                                                                    E5              =                                                (                                      G4                    ⊕                    H4                                    )                                ⊕                F4                                                                                        =                                                (                                      C                    ⊕                    A4                                    )                                ⊕                                  (                                      D                    ⊕                    B4                                    )                                ⊕                F4                                                                                        =                                                (                                      S1                    ⊕                    D84                                    )                                ⊕                                  (                                      S2                    ⊕                    D74                                    )                                ⊕                F4                                                                        (        5        )            
Thus, the correlation between the input data D8 and D7 and the despreading codes S1 and S2 is calculated in the correlation processor 88.
According to the aforementioned construction, the multiplication operation is achieved by the exclusive-OR circuits without using any multipliers. Therefore, the circuit scale is made smaller than that of the prior art of FIG. 12 and the consumption of power can be lowered.
The aforementioned conventional architecture of FIGS. 15 and 16 needs 20 XOR circuits, five AND circuits and four selectors in each of the correlation processors 88, 89, 90 and 91, leading to a large circuit scale. In addition, regarding the number of codes, several hundreds of codes are practically needed although FIG. 15 shows only eight codes. One half of the number of the codes is the number of correlation processors. This leads to an increased circuit scale of the correlation processors, which will in turn, disadvantageously, considerably increase the consumption of power.
If the input data frequently changes like xe2x80x9c010110100101xe2x80x9d, then the signal change is transmitted to all the delay elements 201 through 208. Thus, in this case also, the consumption of power will increase.
Accordingly, the object of the present invention is to solve the aforementioned problems and provide a matched filter capable of suppressing an increase of the circuit scale even if the number of codes increases, by reducing the circuit scale of the correlation processors and restraining the signal change of the delay systems.
In order to achieve the aforementioned object, the present invention provides a matched filter for calculating a correlation value between an input data sequence of a specified length and a code sequence of a specified length, comprising:
a circuit calculating an exclusive-OR of two input data;
a circuit calculating an exclusive-OR of two codes corresponding to the two input data, respectively; and
a correlation calculating means that, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data, calculates a correlation value of the two input data and the two codes.
The provision of the circuit calculating an exclusive-OR of two input data and the circuit calculating an exclusive-OR of two codes corresponding to the two input data, according to the present invention, contributes to the simplification of the logic of the correlation calculating means (which, in one embodiment, comprises one or more correlation processors), and hence the reduction of the circuit scale of the correlation calculating means.
In one embodiment, the correlation calculating means calculates correlation values for a plurality of pairs of input data, said plurality of pairs of input data including at least one pair of consecutive input data.
In this case, the circuit calculating an exclusive-OR of two input data may include a plurality of circuits associated with each other to calculate the exclusive-OR of two input data in each of the plurality of pairs. Also, the circuit calculating an exclusive-OR of two codes may include a plurality of circuits each calculating an exclusive-OR of two codes corresponding to two input data in a pair. Then, the correlation calculating means may comprise a plurality of correlation processors each calculating a correlation value of two input data in a pair and two codes corresponding to the two input data, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data.
In this embodiment, because the two input data of at least one pair are consecutive input data, the configuration of the circuit calculating the exclusive-OR of these two input data can be simplified.
The plurality of pairs of input data may include two or more sequential pairs each consisting of two consecutive input data. In this case, the two consecutive input data in one pair and the two consecutive input data in a next pair also constitute consecutive input data. Then, the correlation calculating means sequentially uses the calculated exclusive-ORs of the pairs of consecutive two input data for the calculation of the correlation values.
Preferably, each of the plurality of pairs of input data may consist of two consecutive input data. This arrangement will obviate the need of executing an exclusive-OR operation of a new combination of input data.
In one embodiment, the exclusive-OR of the two input data and the one of the two input data are delayed by different delay systems, each of which includes delay elements.
In this case, the connection to the correlation calculating means can be simply achieved, and the signal change of the delay systems can be restrained, allowing the data to be shifted with a clock of a frequency lower than the frequency of change of the input data.
An identical clock may be used for delay elements subsequent to an initial delay element of each delay system. In this case, wiring for the clock can be easily made.
Further, an initial delay element of at least one delay system may be supplied with a result of a logic operation of outputs from other delay elements. This can obviate the need for increasing the number of delay elements.
In one embodiment, the delay systems include two or more delay systems delaying the exclusive-OR of the two input data and/or two or more delay systems delaying the one of the two input data.
With this arrangement, the clock frequency can be lowered.
In one embodiment, the correlation calculating means includes an operation means calculating an exclusive-OR of the exclusive-OR of the two input data and the exclusive-OR of the two codes corresponding to the two input data. Thus the correlation calculation or processing can be easily done. The operation means may comprise a plurality of exclusive-OR circuits.
The matched filter according to the present invention can be built in a large-scale integrated circuit. By so doing, the circuit scale and the consumption of power of the large-scale integrated circuit can be reduced.
Also, the large-scale integrated circuit incorporating the matched filter of the present invention can be used as a component of a communication system. In this case, the consumption of power of the communication system can be reduced.
Other objects, features and advantages of the present invention will be obvious from the following description.